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1 mo agofound 3 h ago
Experienced RTL Design Engineer (3+ Years of Experience)
What the posting is about
Design and implement PAD/PFC logic for SoC products using in-house tools. Collaborate with cross-functional teams to ensure design quality. Improve design productivity through automation scripts. Support PAD integration and signoff activities.
Read out of the posting
LevelNot stated
Experience asked3+ years
EmploymentFull time
LocationHo Chi Minh, Vietnam
RemoteNot stated
Visa sponsorshipNot stated
SalaryNot published, and most postings do not
Posted2026-08-18
Found viasmartrecruiters, direct from their system
We saw it 2 months after it went up.
The posting, as the company wrote it
Employment: Full-time
Experience level: Associate
Job Description
Design and implement PAD/PFC logic for SoC products, including pin multiplexing, boundary scan, test functions, and I/O control logic using in-house PAD design tools and methodologies.
Implement PAD logic based on design specifications, pinmux definitions, PAD-RTL/PAD-IO requirements, and integration guidelines.
Generate, integrate, and validate PAD logic using in-house tools (e.g., PGA, SCAAPII), ensuring consistency between specifications and generated design outputs.
Analyze and resolve design issues identified by RTL lint, CDC, synthesis, timing, and formal verification tools.
Develop automation scripts using Python and Tcl to improve design productivity and flow efficiency.
Review verification, formal verification, and signoff results to ensure design quality and completeness.
Collaborate with verification, DFT, STA, backend, and architecture teams throughout the design lifecycle.
Support PAD integration, signoff activities, and continuous improvement of PAD design methodologies and environments.
Job Requirement:
 Strong RTL design experience using Verilog/SystemVerilog.
Understanding of digital design fundamentals, pin multiplexing, and I/O control logic.
Good Python scripting skills; Tcl knowledge is a plus.
Experience with SpyGlass Lint & CDC, synthesis (Genus/DC), and timing analysis tools (PrimeTime)
Knowledge of formal verification (JG-CONN/JG-CSV/JG-FPV) is an advantage.
Basic understanding of DFT, boundary scan, and backend implementation is a plus.
Strong self-learning capability and ability to work with in-house design tools.
Agile problem-solving, transparent communication, and strong collaboration skills.
Ownership mindset with a focus on design quality and continuous improvement.
Qualifications
 
Additional Information
Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier . With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.
At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.
We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.
Are you ready to join our team and shape the future with us?
Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our  Diversity & Inclusion Statement .
Also open at Renesas
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