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Principal FPGA Engineer
Posted by CesiumAstro on 15 October 2026. Still on their Lever board when we checked 11 min ago. Half of CesiumAstro's roles come down within 102 days.
What the posting is about
Design and develop FPGA circuits and systems for satellites, spacecraft, and aerospace platforms. Present engineering design reviews and participate in proposal-writing efforts.
Read out of the posting
LevelNot stated
Experience asked5+ years
EmploymentNot stated
LocationWestminster, CO
RemoteNot stated
Visa sponsorshipNo
SalaryNot published, and most postings do not
Posted2026-10-15
Found vialever, direct from their system
We had it within the hour it went up.
The posting, as the company wrote it
Please Note: To conform with the United States Government Space Technology Export Regulations, the applicant must be a U.S. citizen, lawful permanent resident of the U.S., conditional resident, asylee or refugee (protected individuals as defined by 8 U.S.C. 1324b(a)(3)), or eligible to obtain the required authorizations from the U.S. Department of State.
At CesiumAstro, we are developers and pioneers of out-of-the-box communication systems for satellites, UAVs, launch vehicles, and other space and airborne platforms. We take pride in our dynamic and cross-functional work environment, which allows us to learn, develop, and engage across our organization. If you are looking for hands-on, interactive, and autonomous work, CesiumAstro is the place for you. We are actively seeking passionate, collaborative, energetic, and forward-thinking individuals to join our team.
We are looking to add a Principal FPGA Engineer I to our team. If you enjoy working in a startup environment, and are passionate about developing leading-edge hardware for satellites, spacecraft, and aerospace systems, we would like to hear from you.
In this position, you will be responsible for FPGA circuits and systems through all phases of the development process. The ideal candidate will have experience in FPGA design, verification, test, and deployment at the HDL level. FPGA HDL designs will include high-speed serial interfaces and data streams, digital processing cores, multiple clocks and clock domains, and management interfaces. Testing, validation, and verification will also be central tasks for any FPGA design. Experience in digital signal processing or board-level hardware design is also helpful in the role.
As a principal level employee, you will present engineering design review materials to our customers and executive team, as well as participate in proposal-writing efforts. As such, excellent written and verbal communication skills are required.
Copied from CesiumAstro’s own board, not rewritten. Original ↗
Also open at CesiumAstro
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