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(Senior) Layout Engineer (f/m/d)
Posted by Renesas on 13 October 2026. Still on their SmartRecruiters board when we checked 23 min ago. Half of Renesas's roles come down within 15 days.
Read out of the posting
LevelNot stated
Experience askedNot stated
EmploymentNot stated
LocationBingen, Germany
RemoteNot stated
Visa sponsorshipNot stated
SalaryNot published, and most postings do not
Posted2026-10-13
Found viasmartrecruiters, direct from their system
We saw it 7 hours after it went up.
The posting, as the company wrote it
Employment: Full-time
Experience level: Mid-Senior Level
Job Description
To further strengthen our Automotive Sensors business comprising Sensor ASICs, Sensor ASSPs, Position Sensors, LiDAR ASICs and Environmental Sensors, we are currently looking for an Analog IC Layout Engineer (F/M/D) to join our engineering team in Dresden, Munich or Bingen am Rhein, Germany, for developing our new and next generation ICs, integrated sensors, innovations, power and mixed signal technologies besides supporting modifications to existing products. 
 
Your Role: 
Create block-level and top-level layout design and implement them according to Renesas product development process following best practices from the industry 
Own layout design for multiple tape outs of ICs and test structures 
Implementation of the chip level layout requirements with efficiency and accuracy using industry standard design flows - parameterized layout, LVS, DRC and DFM 
Support block-level and top-level specifications 
Implement analog layout dependent design for yield and manufacturability 
Ensure block- and top-level Design Rule Checks (DRC) and Layout versus Schematics Checks (LVS). 
Ensure optimized silicon COGS and deliver optimized layouts that are first time right 
Qualifications
Your Profile: 
Degree in Electrical Engineering, Electronics, Microelectronics, Microsystems or similar 
Fundamental knowledge on Semiconductor Device Physics and Microelectronics is required 
Experience with Cadence Virtuoso and other Cadence tools 
Experience with layout verification using Calibre DRC and LVS layout verification tools 
Experience with parasitic extraction using Calibre and Cadence tools and their analysis. 
High level of self-motivation, drive, open-mindedness and teamwork skills are desired 
Good communication and technical reporting skills, both written and oral 
Fluent English and German knowledge would be a plus 
Additional Information
Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier . With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.
At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.
We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.
Are you ready to join our team and shape the future with us?
Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our  Diversity & Inclusion Statement .
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