Senior/Staff Verification Engineer

Employment: Full-time Experience level: Mid-Senior Level Job Description We are looking for an experienced Senior or Staff Verification Engineer to play a key role in the functional verification of complex digital ICs for automotive and industrial applications. In this role, you will drive verification activities from requirements analysis through coverage-driven sign-off, leveraging strong SystemVerilog/UVM expertise while contributing to reusable methodologies, process improvements, and the growth of less-experienced team members. Key Responsibilities Analyze product requirements, architectures, and design specifications to define verification strategies, risks, dependencies, and acceptance criteria. Create and maintain verification plans, ensuring clear requirements traceability, coverage objectives, and sign-off readiness. Develop and enhance reusable SystemVerilog/UVM verification environments, including agents, sequences, scoreboards, reference models, and coverage solutions. Design and execute constrained-random, directed, error-injection, assertion-based, and formal verification test scenarios. Drive regressions, debug verification and design issues, collaborate closely with design engineers, and ensure timely defect closure. Measure, analyze, and close functional, code, and assertion coverage gaps to achieve verification quality and sign-off goals. Contribute to system-level verification, technical reviews, automation initiatives, continuous improvement efforts, and mentoring of junior engineers. Qualifications Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent industry experience. 5+ years of digital functional verification experience (or 3+ years with a relevant Master's degree). Strong expertise in SystemVerilog and hands-on experience developing and debugging UVM-based verification environments. Solid understanding of constrained-random, coverage-driven verification methodologies, regression management, and verification planning. Experience translating specifications into verification plans, coverage models, test strategies, and verification reports. Good knowledge of digital design fundamentals, interfaces, clock/reset architectures, simulation, and debug workflows; experience with SVA and/or formal verification is a plus. Strong communication, collaboration, and mentoring skills, with the ability to work independently in a team environment; fluent in spoken and written English. Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier . With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future. At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives. We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process. Are you ready to join our team and shape the future with us? Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our  Diversity & Inclusion Statement .