Posted 2 d ago
Staff Test Engineer
·Edinburgh, United Kingdom·via SmartRecruiters
Posted by Renesas on 12 November 2026, 2 days ago. Still on their SmartRecruiters board when we checked 6 min ago. Renesas has posted this exact title 3 times before. Half of Renesas's roles come down within 20 days.
Mid-Senior LevelFull time
What the posting is about
The role involves designing and developing software and hardware test solutions for mixed-signal ICs using tools like Advantest V93K and Teradyne UltraFLEX. Responsibilities include implementing reliable test strategies, leading projects, and mentoring junior engineers in a fast-paced test engineering team. Experience with ATE systems and mixed-signal test methodologies is essential for this position.
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Read out of the posting
LevelMid-Senior Level
Experience askedNot stated
EmploymentFull time
LocationEdinburgh, United Kingdom
Work arrangementNot stated
Visa sponsorshipNot stated
SalaryNot extracted, check the posting
Posted2026-11-12
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The posting, as the company wrote it
Employment: Full-time
Experience level: Mid-Senior Level
Job Description
Define innovative, efficient test strategies for our mixed-signal ICs, working closely with our Design and Design-For-Test Department.
Design and develop software and hardware test solutions for state-of-the-art mixed signal ATE systems, for both silicon characterization and production testing.
Implement, correlate, and release reliable test solutions at our production facilities, and support mass-production ramp.
Drive technical innovation in the department.
Lead the Test Development project.
Mentor, guide, and train junior Test Engineering members.
Qualifications
Engineering degree in Electronics Engineering or equivalent education.
Proven experience in ATE Test development for analogue and mixed signal ICs.
Hands-on experience on Advantest V93K, Cohu DiamondX(DMDX) and/or Teradyne UltraFLEX or equivalent mixed signal ATE.
Strong technical knowledge of electronic devices and circuits, mixed signal test techniques/methodologies.
Good technical knowledge of various Design-for-Test techniques and methodologies.
Experience with hardware and PCB design tools.
Experience with lab equipment such as oscilloscopes, digital multi-meters, VIPER, etc.
Proficient in statistical analysis and data analysis tools.
Understanding of GIT or similar revision control.
Good verbal and written communication skills.
Ability to collaborated effectively in teams and across functions.
Experience mentoring and leading junior team members.
Additional Information
Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier . With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.
At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.
We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.
Are you ready to join our team and shape the future with us?
Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement .
Company Description
Join our fast-paced, results-driven Test Engineering Team. We develop innovative, cost-efficient software and hardware ATE solutions for production and qualification of high volume Power Management ICs.
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